Single instruction, multiple threads

Single instruction, multiple thread (SIMT) is an execution model used in parallel computing where single instruction, multiple data (SIMD) is combined with multithreading.

Overview

The processors, say a number p of them, seem to execute many more than p tasks. This is achieved by each processor having multiple "threads" (or "work-items" or "Sequence of SIMD Lane operations"), which execute in lock-step, and are analogous to SIMD lanes.[1]

The SIMT execution model has been implemented on several GPUs and is relevant for general-purpose computing on graphics processing units (GPGPU), e.g. some supercomputers combine CPUs with GPUs.

SIMT was introduced by Nvidia:[2][3]

Nvidia's Tesla GPU microarchitecture (first available November 8, 2006 as implemented in the "G80" GPU chip) introduced the single-instruction multiple-thread (SIMT) execution model where multiple independent threads execute concurrently using a single instruction.

ATI Technologies (now AMD) released a competing product slightly later on May 14, 2007, the TeraScale 1-based "R600" GPU chip.

As access time of all the widespread RAM types (e.g. DDR SDRAM, GDDR SDRAM, XDR DRAM, etc.) is still relatively high, engineers came up with the idea to hide the latency that inevitably comes with each memory access. Strictly, the latency-hiding is a feature of the zero-overhead scheduling implemented by modern GPUs. This might or might not be considered to be a property of 'SIMT' itself.

SIMT is intended to limit instruction fetching overhead,[4] i.e. the latency that comes with memory access, and is used in modern GPUs (such as those of Nvidia and AMD) in combination with 'latency hiding' to enable high-performance execution despite considerable latency in memory-access operations. This is where the processor is oversubscribed with computation tasks, and is able to quickly switch between tasks when it would otherwise have to wait on memory. This strategy is comparable to multithreading in CPUs (not to be confused with multi-core).[5]

A downside of SIMT execution is the fact that thread-specific control-flow is performed using "masking", leading to poor utilization where a processor's threads follow different control-flow paths. For instance, to handle an IF-ELSE block where various threads of a processor execute different paths, all threads must actually process both paths (as all threads of a processor always execute in lock-step), but masking is used to disable and enable the various threads as appropriate. Masking is avoided when control flow is coherent for the threads of a processor, i.e. they all follow the same path of execution. The masking strategy is what distinguishes SIMT from ordinary SIMD, and has the benefit of inexpensive synchronization between the threads of a processor.[6]

Nvidia CUDA OpenCL Henn&Patt
Thread Work-item Sequence of SIMD Lane operations
Warp Wavefront Thread of SIMD Instructions
Block Workgroup Body of vectorized loop
Grid NDRange Vectorized loop
See also
References
  1. Michael McCool; James Reinders; Arch Robison (2013). Structured Parallel Programming: Patterns for Efficient Computation. Elsevier. p. 52.
  2. "Nvidia Fermi Compute Architecture Whitepaper" (PDF). http://www.nvidia.com/. NVIDIA Corporation. 2009. Retrieved 2014-07-17.
  3. "NVIDIA Tesla: A Unified Graphics and Computing Architecture". IEEE Micro. IEEE. 28: 6 (Subscription required.). 2008. doi:10.1109/MM.2008.31.
  4. Rul, Sean; Vandierendonck, Hans; D’Haene, Joris; De Bosschere, Koen (2010). An experimental study on performance portability of OpenCL kernels. Symp. Application Accelerators in High Performance Computing (SAAHPC).
  5. "Advanced Topics in CUDA" (PDF). cc.gatech.edu. 2011. Retrieved 2014-08-28.
  6. Michael McCool; James Reinders; Arch Robison (2013). Structured Parallel Programming: Patterns for Efficient Computation. Elsevier. pp. 209 ff.
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ARM architecture

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ARM architecture

ARM, previously Advanced RISC Machine, originally Acorn RISC Machine, is a family of reduced instruction set computing (RISC) architectures for computer processors, configured for various environments. Arm Holdings develops the architecture and licenses it to other companies, who design their own products that implement one of those architectures‍—‌including systems-on-chips (SoC) and systems-on-modules (SoM) that incorporate memory, interfaces, radios, etc. It also designs cores that implement this instruction set and licenses these designs to a number of companies that incorporate those core designs into their own products. Processors that have a RISC architecture typically require fewer transistors than those with a complex instruction set computing (CISC) architecture (such as the x86 processors found in most personal computers), which improves cost, power consumption, and heat dissipation. These characteristics are desirable for light, portable, battery-powered devices‍—‌including smartphones, laptops a ...more...

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Context switch

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Context switch

The process of a Context Switch In computing, a context switch is the process of storing the state of a process or of a thread, so that it can be restored and execution resumed from the same point later. This allows multiple processes to share a single CPU, and is an essential feature of a multitasking operating system. The precise meaning of the phrase “context switch” varies significantly in usage. In a multitasking context, it refers to the process of storing the system state for one task, so that task can be paused and another task resumed. A context switch can also occur as the result of an interrupt, such as when a task needs to access disk storage, freeing up CPU time for other tasks. Some operating systems also require a context switch to move between user mode and kernel mode tasks. The process of context switching can have a negative impact on system performance, although the size of this effect depends on the nature of the switch being performed. Cost Context switches are usually computationall ...more...

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Von Neumann programming languages

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Von Neumann programming languages

A von Neumann language is any of those programming languages that are high-level abstract isomorphic copies of von Neumann architectures. As of 2009, most current programming languages fit into this description, likely as a consequence of the extensive domination of the von Neumann computer architecture during the past 50 years. The differences between Fortran, C, and even Java, although considerable, are ultimately constrained by all three being based on the programming style of the von Neumann computer. If, for example, Java objects were all executed in parallel with asynchronous message passing and attribute-based declarative addressing, then Java would not be in the group. The isomorphism between von Neumann programming languages and architectures is in the following manner: program variables ↔ computer storage cells control statements ↔ computer test-and-jump instructions assignment statements ↔ fetching, storing instructions expressions ↔ memory reference and arithmetic instructions. Criticism ...more...

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Reentrancy (computing)

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Reentrancy (computing)

In computing, a computer program or subroutine is called reentrant if it can be interrupted in the middle of its execution and then safely be called again ("re-entered") before its previous invocations complete execution. The interruption could be caused by an internal action such as a jump or call, or by an external action such as an interrupt or signal. Once the reentered invocation completes, the previous invocations will resume correct execution. This definition originates from single-threaded programming environments where the flow of control could be interrupted by an interrupt and transferred to an interrupt service routine (ISR). Any subroutine used by the ISR that could potentially have been executing when the interrupt was triggered should be reentrant. Often, subroutines accessible via the operating system kernel are not reentrant. Hence, interrupt service routines are limited in the actions they can perform; for instance, they are usually restricted from accessing the file system and sometimes ev ...more...

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Coffee Lake

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Coffee Lake

Coffee Lake is Intel's codename for the second 14 nm process refinement following Broadwell, Skylake, and Kaby Lake.[2] The integrated graphics on Coffee Lake chips allow support for DP 1.2 to HDMI 2.0 and HDCP 2.2 connectivity. Coffee Lake natively supports DDR4-2666 MHz memory in dual channel mode. Desktop Coffee Lake CPUs introduce a major change in Intel's Core CPUs nomenclature, in that i5 and i7 CPUs feature six cores (along with hyper-threading in the case of the latter). i3 CPUs, having four cores and dropping hyper-threading for the first time, received a change as well. The chips were released on October 5, 2017.[1] Coffee Lake will be used in conjunction with the 300-series chipset, and will not work with the 100- and 200-series chipsets. Although desktop Coffee Lake processors use the same physical LGA 1151 socket as Skylake and Kaby Lake, the pinout is electrically incompatible with these older processors and motherboards.[3] On April 2, 2018 Intel released additional desktop Core i3, i5, i7, ...more...

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MAJC

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MAJC

MAJC (Microprocessor Architecture for Java Computing) was a Sun Microsystems multi-core, multithreaded, very long instruction word (VLIW) microprocessor design from the mid-to-late 1990s. Originally called the UltraJava processor, the MAJC processor was targeted at running Java programs, whose "late compiling" allowed Sun to make several favourable design decisions. The processor was released into two commercial graphical cards from Sun. Lessons learned regarding multi-threads on a multi-core processor provided a basis for later OpenSPARC implementations such as the UltraSPARC T1. Design elements Move instruction scheduling to the compiler Like other VLIW designs, notably Intel's IA-64 (Itanium), MAJC attempted to improve performance by moving several expensive operations out of the processor and into the related compilers. In general, VLIW designs attempt to eliminate the instruction scheduler, which often represents a relatively large amount of the overall processor's transistor budget. With this portion ...more...

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Microarchitecture

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Microarchitecture

Intel Core microarchitecture In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA), is implemented in a particular processor.[1] A given ISA may be implemented with different microarchitectures;[2][3] implementations may vary due to different goals of a given design or due to shifts in technology.[4] Computer architecture is the combination of microarchitecture and instruction set architecture. Relation to instruction set architecture A microarchitecture organized around a single bus The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machin ...more...

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Task parallelism

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Task parallelism

Task parallelism (also known as function parallelism and control parallelism) is a form of parallelization of computer code across multiple processors in parallel computing environments. Task parallelism focuses on distributing tasks—concurrently performed by processes or threads—across different processors. In contrast to data parallelism which involves running the same task on different components of data, task parallelism is distinguished by running many different tasks at the same time on the same data.[1] A common type of task parallelism is pipelining which consists of moving a single set of data through a series of separate tasks where each task can execute independently of the others. Description In a multiprocessor system, task parallelism is achieved when each processor executes a different thread (or process) on the same or different data. The threads may execute the same or different code. In the general case, different execution threads communicate with one another as they work, but is not a re ...more...

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DragonFly BSD

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DragonFly BSD

DragonFly BSD is a free and open source Unix-like operating system created as a fork of FreeBSD 4.8. Matthew Dillon, an Amiga developer in the late 1980s and early 1990s and a FreeBSD developer between 1994 and 2003, began work on DragonFly BSD in June 2003 and announced it on the FreeBSD mailing lists on 16 July 2003.[3] Dillon started DragonFly in the belief that the methods and techniques being adopted for threading and symmetric multiprocessing in FreeBSD 5[4] would lead to poor system performance and cause maintenance difficulties. He sought to correct these suspected problems within the FreeBSD project.[5] Due to ongoing conflicts with other FreeBSD developers over the implementation of his ideas,[6] his ability to directly change the FreeBSD codebase was eventually revoked. Despite this, the DragonFly BSD and FreeBSD projects still work together contributing bug fixes, driver updates, and other system improvements to each other. Intended to be the logical continuation of the FreeBSD 4.x series, Drago ...more...

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Pascal (microarchitecture)

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Pascal (microarchitecture)

Pascal is the codename for a GPU microarchitecture developed by Nvidia, as the successor to the Maxwell architecture. The architecture was first introduced in April 2016 with the release of the Tesla P100 (GP100) on April 5, 2016, and is primarily used in the GeForce 10 series, starting with the GeForce GTX 1080 and GTX 1070 (both using the GP104 GPU), which were released on May 17, 2016 and June 10, 2016 respectively. Pascal is manufactured using the 16nm FinFET process. The architecture is named after the 17th century French mathematician and physicist, Blaise Pascal. Details In March 2014, Nvidia announced that the successor to Maxwell would be the Pascal microarchitecture; announced on 6 May 2016 and released on 27 May 2016. The Tesla P100 (GP100 chip) has a different version of the Pascal architecture compared to the GTX GPUs (GP104 chip). The shader units in GP104 have a Maxwell-like design.[1] Architectural improvements of the GP100 architecture include the following:[2][3][4] In Pascal, an SM (s ...more...

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Java ConcurrentMap

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Java ConcurrentMap

The Java programming language's Java Collections Framework version 1.5 and later defines and implements the original regular single-threaded Maps, and also new thread-safe Maps implementing the java.util.concurrent.ConcurrentMapinterface among other concurrent interfaces. In Java 1.6, the java.util.NavigableMap interface was added, extending java.util.SortedMap, and the java.util.concurrent.ConcurrentNavigableMap interface was added as a subinterface combination. Java Map Interfaces The version 1.8 Map interface diagram has the shape below. Sets can be considered sub-cases of corresponding Maps in which the values are always a particular constant which can be ignored, although the Set API uses corresponding but differently named methods. At the bottom is the java.util.concurrent.ConcurrentNavigableMap, which is a multiple-inheritance. java.util.Collection java.util.Map java.util.SortedMap java.util.NavigableMap java.util.concurrent.ConcurrentNavigableMap java.util.concurrent.ConcurrentMap ...more...

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Register file

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Register file

A register file is an array of processor registers in a central processing unit (CPU). Modern integrated circuit-based register files are usually implemented by way of fast static RAMs with multiple ports. Such RAMs are distinguished by having dedicated read and write ports, whereas ordinary multiported SRAMs will usually read and write through the same ports. The instruction set architecture of a CPU will almost always define a set of registers which are used to stage data between memory and the functional units on the chip. In simpler CPUs, these architectural registers correspond one-for-one to the entries in a physical register file (PRF) within the CPU. More complicated CPUs use register renaming, so that the mapping of which physical entry stores a particular architectural register changes dynamically during execution.[1] The register file is part of the architecture and visible to the programmer, as opposed to the concept of transparent caches. Register bank switching Register files may be clubbed t ...more...

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Athlon 64 X2

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Athlon 64 X2

The Athlon 64 X2 is the first native dual-core desktop CPU designed by AMD. It was designed from scratch as native dual-core by using an already multi-CPU enabled Athlon 64, joining it with another functional core on one die, and connecting both via a shared dual-channel memory controller/north bridge and additional control logic. The initial versions are based on the E-stepping model of the Athlon 64 and, depending on the model, have either 512 or 1024 KB of L2 Cache per core. The Athlon 64 X2 is capable of decoding SSE3 instructions (except those few specific to Intel's architecture). In June 2007, AMD released low-voltage variants of their low-end 65 nm Athlon 64 X2, named "Athlon X2".[1] The Athlon X2 processors feature reduced TDP of 45 W.[2] The name was also used for K10 based budget CPUs with two cores deactivated. Multithreading The primary benefit of dual-core processors (like the Athlon 64 X2) over single-core processors is their ability to process more software threads at the same time. The abi ...more...

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Coroutine

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Coroutine

Coroutines are computer-program components that generalize subroutines for non-preemptive multitasking, by allowing multiple entry points for suspending and resuming execution at certain locations. Coroutines are well-suited for implementing familiar program components such as cooperative tasks, exceptions, event loops, iterators, infinite lists and pipes. According to Donald Knuth, Melvin Conway coined the term coroutine in 1958 when he applied it to construction of an assembly program.[1] The first published explanation of the coroutine appeared later, in 1963.[2] Comparison with subroutines Subroutines are special cases of coroutines.[3] When subroutines are invoked, execution begins at the start, and once a subroutine exits, it is finished; an instance of a subroutine only returns once, and does not hold state between invocations. By contrast, coroutines can exit by calling other coroutines, which may later return to the point where they were invoked in the original coroutine; from the coroutine's poin ...more...

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Monitor (synchronization)

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Monitor (synchronization)

In concurrent programming, a monitor is a synchronization construct that allows threads to have both mutual exclusion and the ability to wait (block) for a certain condition to become true. Monitors also have a mechanism for signaling other threads that their condition has been met. A monitor consists of a mutex (lock) object and condition variables. A condition variable is basically a container of threads that are waiting for a certain condition. Monitors provide a mechanism for threads to temporarily give up exclusive access in order to wait for some condition to be met, before regaining exclusive access and resuming their task. Another definition of monitor is a thread-safe class, object, or module that wraps around a mutex in order to safely allow access to a method or variable by more than one thread. The defining characteristic of a monitor is that its methods are executed with mutual exclusion: At each point in time, at most one thread may be executing any of its methods. By using one or more conditio ...more...

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Very long instruction word

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Very long instruction word

Very long instruction word (VLIW) refers to instruction set architectures designed to exploit instruction level parallelism (ILP). Whereas conventional central processing units (CPU, processor) mostly allow programs to specify instructions to execute in sequence only, a VLIW processor allows programs to explicitly specify instructions to execute in parallel. This design is intended to allow higher performance without the complexity inherent in some other designs. Overview The traditional means to improve performance in processors include dividing instructions into substeps so the instructions can be executed partly at the same time (termed pipelining), dispatching individual instructions to be executed independently, in different parts of the processor (superscalar architectures), and even executing instructions in an order different from the program (out-of-order execution). These methods all complicate hardware (larger circuits, higher cost and energy use) because the processor must make all of the decisi ...more...

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Duff's device

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Duff's device

In the C programming language, Duff's device is a way of manually implementing loop unrolling by interleaving two syntactic constructs of C: the do-while loop and a switch statement. Its discovery is credited to Tom Duff in November 1983, when Duff was working for Lucasfilm and used it to speed up a real-time animation program. Loop unrolling attempts to reduce the overhead of conditional branching needed to check whether a loop is done, by executing a batch of loop bodies per iteration. To handle cases where the number of iterations is not divisible by the unrolled-loop increments, a common technique among assembly language programmers is to jump directly into the middle of the unrolled loop body to handle the remainder.[1] Duff implemented this technique in C by using C's case label fall-through feature to jump into the unrolled body.[2] Original version Duff's problem was to copy 16-bit units ("shorts" in most C implementations) from an array into a memory-mapped output register, denoted in C by a point ...more...

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Task (computing)

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Task (computing)

A sample thread pool (green boxes) with task queues of waiting tasks (blue) and completed tasks (yellow), in the sense of task as "unit of work". In computing, a task is a unit of execution or a unit of work. The term is ambiguous; precise alternative terms include process, light-weight process, thread (for execution), step, request, or query (for work). In the adjacent diagram, there are queues of incoming work to do and outgoing completed work, and a thread pool of threads to perform this work. Either the work units themselves or the threads that perform the work can be referred to as "tasks", and these can be referred to respectively as requests/responses/threads, incoming tasks/completed tasks/threads (as illustrated), or requests/responses/tasks. Terminology In the sense of "unit of execution", in some operating systems, a task is synonymous with a process, and in others with a thread. In non-interactive execution (batch processing), a task is a unit of execution within a job,[1][2] with the task its ...more...

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JTAG

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JTAG

JTAG (named after the Joint Test Action Group which codified it) is an industry standard for verifying designs and testing printed circuit boards after manufacture. JTAG implements standards for on-chip instrumentation in electronic design automation (EDA) as a complementary tool to digital simulation.[1] It specifies the use of a dedicated debug port implementing a serial communications interface for low-overhead access without requiring direct external access to the system address and data buses. The interface connects to an on-chip test access port (TAP) that implements a stateful protocol to access a set of test registers that present chip logic levels and device capabilities of various parts. The Joint Test Action Group formed in 1985 to develop a method of verifying designs and testing printed circuit boards after manufacture. In 1990 the Institute of Electrical and Electronics Engineers codified the results of the effort in IEEE Standard 1149.1-1990, entitled Standard Test Access Port and Boundary-Sc ...more...

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Glossary of operating systems terms

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Glossary of operating systems terms

This page is a glossary of Operating systems terminology.[1][2] A access token: In Microsoft Windows operating systems, an access token contains the security credentials for a login session and identifies the user, the user's groups, the user's privileges, and, in some cases, a particular application. B binary semaphore: See semaphore. booting: In computing, booting (also known as booting up) is the initial set of operations that a computer system performs after electrical power to the CPU is switched on or when the computer is reset. On modern general purpose computers, this can take tens of seconds and typically involves performing a power-on self-test, locating and initializing peripheral devices, and then finding, loading and starting the operating system. C cache: In computer science, a cache is a component that transparently stores data so that future requests for that data can be served faster. The data that is stored within a cache might be values that have been computed earlier or du ...more...

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List of Intel microprocessors

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List of Intel microprocessors

Intel Haswell Core i7-4771 CPU, sitting atop its original packaging that contains an OEM fan-cooled heatsink This generational list of Intel processors attempts to present all of Intel's processors from the pioneering 4-bit 4004 (1971) to the present high-end offerings, which include the 64-bit Itanium 2 (2002), Intel Core i9, and Xeon E3 and E5 series processors (2015). Concise technical data is given for each product. Latest desktop and mobile processors for consumers 8th generation Core/Coffee Lake/Kaby Lake Refresh Desktop Model Price (USD) Cores/Threads Base frequency (GHz) Max turbo frequency (GHz) GPU Maximum GPU clock rate (MHz) L3 cache (MB) TDP (W) Socket Release i7-8086K $425 6/12 4.0 5.0 UHD 630 1200 12 95 LGA 1151 Q2 2018 i7-8700k $359 6/12 3.7 4.7 UHD 630 1200 12 95 LGA 1151 Q4 2017 i7-8700 $303 6/12 3.2 4.6 UHD 630 1200 12 65 LGA 1151 Q4 2017 i5-8600K $257 6/6 3.6 4.3 UHD 630 1150 9 95 LGA 1151 Q4 2017 i5-8400 $1 ...more...

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Mutual exclusion

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Mutual exclusion

Two nodes, i and i + 1, being removed simultaneously results in node i + 1 not being removed. In computer science, mutual exclusion is a property of concurrency control, which is instituted for the purpose of preventing race conditions; it is the requirement that one thread of execution never enter its critical section at the same time that another concurrent thread of execution enters its own critical section.[a] The requirement of mutual exclusion was first identified and solved by Edsger W. Dijkstra in his seminal 1965 paper titled Solution of a problem in concurrent programming control,[1][2] which is credited as the first topic in the study of concurrent algorithms.[3] A simple example of why mutual exclusion is important in practice can be visualized using a singly linked list of four items, where the second and third are to be removed. The removal of a node that sits between 2 other nodes is performed by changing the next pointer of the previous node to point to the next node (in other words, if no ...more...

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NetBurst (microarchitecture)

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NetBurst (microarchitecture)

The NetBurst microarchitecture,[1][2] called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of CPUs made by Intel. The first CPU to use this architecture was the Willamette-core Pentium 4, released on November 20, 2000 and the first of the Pentium 4 CPUs; all subsequent Pentium 4 and Pentium D variants have also been based on NetBurst. In mid-2004, Intel released the Foster core, which was also based on NetBurst, thus switching the Xeon CPUs to the new architecture as well. Pentium 4-based Celeron CPUs also use the NetBurst architecture. NetBurst was replaced with the Core microarchitecture, released in July 2006. Technology The NetBurst microarchitecture includes features such as Hyper-Threading, Hyper Pipelined Technology, Rapid Execution Engine and Replay System which are were introduced for the first time in this particular microarchitecture. Hyper-Threading Hyper-threading is Intel's proprietary simultaneous multithreading (SMT) implementation used to improve paral ...more...

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Test-and-set

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Test-and-set

In computer science, the test-and-set instruction is an instruction used to write 1 (set) to a memory location and return its old value as a single atomic (i.e., non-interruptible) operation. If multiple processes may access the same memory location, and if a process is currently performing a test-and-set, no other process may begin another test-and-set until the first process's test-and-set is finished. A CPU may use a test-and-set instruction offered by another electronic component, such as dual-port RAM; a CPU itself may also offer a test-and-set instruction. A lock can be built using an atomic test-and-set[1] instruction as follows: function Lock(boolean *lock) { while (test_and_set(lock) == 1); } The calling process obtains the lock if the old value was 0 otherwise while-loop spins waiting to acquire the lock. This is called a spinlock. "Test and Test-and-set" is another example. Maurice Herlihy (1991) proved that test-and-set has a finite consensus number and can solve the wait-free consensus probl ...more...

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Swap (computer programming)

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Swap (computer programming)

In computer programming, the act of swapping two variables refers to mutually exchanging the values of the variables. Usually, this is done with the data in memory. For example, in a program, two variables may be defined thus (in pseudocode): data_item x := 1 data_item y := 0 swap (x, y); After swap is performed, x will contain the value 0 and y will contain 1; their values have been exchanged. This operation may be generalized to other types of values, such as strings and aggregated data types. Comparison sorts use swaps to change the positions of data. In many programming languages the swap function is built-in. In C++, overloads are provided allowing std::swap to exchange some large structures in O(1) time. Using a temporary variable The simplest and probably most widely used method to swap two variables is to use a third temporary variable: define swap (x, y) temp := x x := y y := temp While this is conceptually simple and in many cases the only convenient way to swap two variables, it uses extra me ...more...

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IBM POWER microprocessors

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IBM POWER microprocessors

IBM has a series of high performance microprocessors called POWER followed by a number designating generation, i.e. POWER1, POWER2, POWER3 and so forth up to the latest POWER9. These processors have been used by IBM in their RS/6000, AS/400, pSeries, iSeries, System p, System i and Power Systems line of servers and supercomputers. They have also been used in data storage devices by IBM and by other server manufacturers like Bull and Hitachi. The name "POWER" was originally presented as an acronym for "Performance Optimization With Enhanced RISC". The POWERn family of processors were developed in the late 1980s and are still in active development nearly 30 years later. In the beginning, they utilized the POWER instruction set architecture (ISA), but that evolved into PowerPC in later generations and then to Power Architecture, so modern POWER processors do not use the POWER ISA, they use the Power ISA. History Early developments The 801 research project In 1974 IBM started a project to build a telephone sw ...more...

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Translation lookaside buffer

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Translation lookaside buffer

A translation lookaside buffer (TLB) is a memory cache that is used to reduce the time taken to access a user memory location.[1][2] It is a part of the chip’s memory-management unit (MMU). The TLB stores the recent translations of virtual memory to physical memory and can be called an address-translation cache. A TLB may reside between the CPU and the CPU cache, between CPU cache and the main memory or between the different levels of the multi-level cache. The majority of desktop, laptop, and server processors include one or more TLBs in the memory-management hardware, and it is nearly always present in any processor that utilizes paged or segmented virtual memory. The TLB is sometimes implemented as content-addressable memory (CAM). The CAM search key is the virtual address, and the search result is a physical address. If the requested address is present in the TLB, the CAM search yields a match quickly and the retrieved physical address can be used to access memory. This is called a TLB hit. If the reques ...more...

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Symmetric multiprocessing

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Symmetric multiprocessing

Diagram of a symmetric multiprocessing system Symmetric multiprocessing (SMP) involves a multiprocessor computer hardware and software architecture where two or more identical processors are connected to a single, shared main memory, have full access to all input and output devices, and are controlled by a single operating system instance that treats all processors equally, reserving none for special purposes. Most multiprocessor systems today use an SMP architecture. In the case of multi-core processors, the SMP architecture applies to the cores, treating them as separate processors. Professor John D. Kubiatowicz considers traditionally SMP systems to contain processors without caches.[1] Culler and Pal-Singh in their 1998 book "Parallel Computer Architecture: A Hardware/Software Approach" mention: "The term SMP is widely used but causes a bit of confusion. [...] The more precise description of what is intended by SMP is a shared memory multiprocessor where the cost of accessing a memory location is the s ...more...

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Classes of computers

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Time Stamp Counter

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Time Stamp Counter

The Time Stamp Counter (TSC) is a 64-bit register present on all x86 processors since the Pentium. It counts the number of cycles since reset. The instruction RDTSC returns the TSC in EDX:EAX. In x86-64 mode, RDTSC also clears the higher 32 bits of RAX and RDX. Its opcode is 0F 31.[1] Pentium competitors such as the Cyrix 6x86 did not always have a TSC and may consider RDTSC an illegal instruction. Cyrix included a Time Stamp Counter in their MII. Use The Time Stamp Counter was once an excellent high-resolution, low-overhead way for a program to get CPU timing information. With the advent of multi-core/hyper-threaded CPUs, systems with multiple CPUs, and hibernating operating systems, the TSC cannot be relied upon to provide accurate results — unless great care is taken to correct the possible flaws: rate of tick and whether all cores (processors) have identical values in their time-keeping registers. There is no promise that the timestamp counters of multiple CPUs on a single motherboard will be synchroniz ...more...

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CPU cache

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CPU cache

A CPU cache[1] is a hardware cache used by the central processing unit (CPU) of a computer to reduce the average cost (time or energy) to access data from the main memory. A cache is a smaller, faster memory, closer to a processor core, which stores copies of the data from frequently used main memory locations. Most CPUs have different independent caches, including instruction and data caches, where the data cache is usually organized as a hierarchy of more cache levels (L1, L2, etc.). All modern (fast) CPUs (with few specialized exceptions[2]) have multiple levels of CPU caches. The first CPUs that used a cache had only one level of cache; unlike later level 1 caches, it was not split into L1d (for data) and L1i (for instructions). Almost all current CPUs with caches have a split L1 cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache is usually not split and acts as a common repository for the already split L1 cache. Every core of a multi-core processor has a dedicate ...more...

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Computer cluster

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Computer cluster

Technicians working on a large Linux cluster at the Chemnitz University of Technology, Germany Sun Microsystems Solaris Cluster A computer cluster is a set of loosely or tightly connected computers that work together so that, in many respects, they can be viewed as a single system. Unlike grid computers, computer clusters have each node set to perform the same task, controlled and scheduled by software. The components of a cluster are usually connected to each other through fast local area networks, with each node (computer used as a server) running its own instance of an operating system. In most circumstances, all of the nodes use the same hardware[1] and the same operating system, although in some setups (e.g. using Open Source Cluster Application Resources (OSCAR)), different operating systems can be used on each computer, or different hardware.[2] Clusters are usually deployed to improve performance and availability over that of a single computer, while typically being much more cost-effective tha ...more...

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Quarterly journals

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SPARC Enterprise

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SPARC Enterprise

The SPARC Enterprise series is a range of UNIX server computers based on the SPARC V9 architecture. It was co-developed by Sun Microsystems and Fujitsu, and introduced in 2007. They were marketed and sold by Sun Microsystems (later Oracle Corporation, after their acquisition of Sun), Fujitsu, and Fujitsu Siemens Computers under the common brand of "SPARC Enterprise", superseding Sun's Sun Fire and Fujitsu's PRIMEPOWER server product lines. Since 2010, servers based on new SPARC CMT processors (SPARC T3 and later) have been branded as Oracle's SPARC T-Series servers. Model range Model Height, RU Max. processors Processor frequency Max. memory Max. disk capacity GA date M3000 2 1× SPARC64 VII or VII+ 2.52, 2.75 GHz (VII) or 2.86 GHz (VII+) 64 GB 4× 2.5-inch SAS October 2008 (2.52 GHz), February 2010 (2.75 GHz), April 2011 (VII+) M4000 6 4× SPARC64 VI or VII or VII+ 2.15 GHz (VI), 2.53 GHz (VII), or 2.66 GHz (VII+) 256 GB 2× 2.5-inch SAS April 2007 (VI), July 2008 (VII), December 2010 (VII+) M5000 ...more...

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Super Harvard Architecture Single-Chip Computer

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Super Harvard Architecture Single-Chip Computer

The Super Harvard Architecture Single-Chip Computer (SHARC) is a high performance floating-point and fixed-point DSP from Analog Devices. SHARC is used in a variety of signal processing applications ranging from single-CPU guided artillery shells to 1000-CPU over-the-horizon radar processing computers. The original design dates to about January 1994. SHARC processors are or were used because they have offered good floating-point performance per watt. SHARC processors are typically intended to have a good number of serial links to other SHARC processors nearby, to be used as a low-cost alternative to SMP. Architecture The SHARC is a Harvard architecture word-addressed VLIW processor; it knows nothing of 8-bit or 16-bit values since each address is used to point to a whole 32-bit word, not just an octet. It is thus neither little-endian nor big-endian, though a compiler may use either convention if it implements 64-bit data and/or some way to pack multiple 8-bit or 16-bit values into a single 32-bit word. A ...more...

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Setcontext

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Setcontext

setcontext is one of a family of C library functions (the others being getcontext, makecontext and swapcontext) used for context control. The setcontext family allows the implementation in C of advanced control flow patterns such as iterators, fibers, and coroutines. They may be viewed as an advanced version of setjmp/longjmp; whereas the latter allows only a single non-local jump up the stack, setcontext allows the creation of multiple cooperative threads of control, each with its own stack. Specification setcontext was specified in POSIX.1-2001 and the Single Unix Specification, version 2, but not all Unix-like operating systems provide them. POSIX.1-2004 obsoleted these functions, and in POSIX.1-2008 they were removed, with POSIX Threads indicated as a possible replacement. Citing IEEE Std 1003.1, 2004 Edition[1]: With the incorporation of the ISO/IEC 9899:1999 standard into this specification it was found that the ISO C standard (Subclause 6.11.6) specifies that the use of function declarators with em ...more...

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Data parallelism

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Data parallelism

Sequential vs. data-parallel job execution Data parallelism is parallelization across multiple processors in parallel computing environments. It focuses on distributing the data across different nodes, which operate on the data in parallel. It can be applied on regular data structures like arrays and matrices by working on each element in parallel. It contrasts to task parallelism as another form of parallelism. A data parallel job on an array of 'n' elements can be divided equally among all the processors. Let us assume we want to sum all the elements of the given array and the time for a single addition operation is Ta time units. In the case of sequential execution, the time taken by the process will be n*Ta time units as it sums up all the elements of an array. On the other hand, if we execute this job as a data parallel job on 4 processors the time taken would reduce to (n/4)*Ta + merging overhead time units. Parallel execution results in a speedup of 4 over sequential execution. One important thing t ...more...

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Multiple dispatch

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Multiple dispatch

Multiple dispatch or multimethods is a feature of some programming languages in which a function or method can be dynamically dispatched based on the run-time (dynamic) type or, in the more general case some other attribute, of more than one of its arguments.[1] This is a generalization of single-dispatch polymorphism where a function or method call is dynamically dispatched based on the actual derived type of the object on which the method has been called. Multiple dispatch routes the dynamic dispatch to the implementing function or method using the combined characteristics of one or more arguments. Understanding dispatch Developers of computer software typically organize source code into named blocks variously called subroutines, procedures, subprograms, functions, or methods. The code in the function is executed by calling it – executing a piece of code that references its name. This transfers control temporarily to the called function; when the function's execution has completed, control is typically tr ...more...

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List of computing and IT abbreviations

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List of computing and IT abbreviations

This is a list of computing and IT acronyms and abbreviations. 0–9 #!—Shebang /.—Slashdot 1GL—First-Generation Programming Language 1NF—First Normal Form 10B2—10BASE-2 10B5—10BASE-5 10B-F—10BASE-F 10B-FB—10BASE-FB 10B-FL—10BASE-FL 10B-FP—10BASE-FP 10B-T—10BASE-T 100B-FX—100BASE-FX 100B-T—100BASE-T 100B-TX—100BASE-TX 100BVG—100BASE-VG 286—Intel 80286 processor 2B1Q—2 Binary 1 Quaternary 2FA—Two-factor authentication 2GL—Second-Generation Programming Language 2NF—Second Normal Form 3GL—Third-Generation Programming Language 3GPP—3rd Generation Partnership Project—'3G comms 3GPP2—3rd Generation Partnership Project 2 3NF—Third Normal Form 386—Intel 80386 processor 486—Intel 80486 processor 4B5BLF—4 Byte 5 Byte Local Fiber 4GL—Fourth-Generation Programming Language 4NF—Fourth Normal Form 5GL—Fifth-Generation Programming Language 5NF—Fifth Normal Form 6NF—Sixth Normal Form 8B10BLF—8 Byte 10 Byte Local Fiber 802.11—Wireless LAN A AAA—Authe ...more...

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Lists of abbreviations

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general

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Microcode

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Microcode

Microcode is a computer hardware technique that imposes an interpreter between the CPU hardware and the programmer-visible instruction set architecture of the computer.[1] As such, the microcode is a layer of hardware-level instructions that implement higher-level machine code instructions or internal state machine sequencing in many digital processing elements. Microcode is used in general-purpose central processing units, although in current desktop CPUs it is only a fallback path for cases that the faster hardwired control unit cannot handle.[2] Microcode typically resides in special high-speed memory and translates machine instructions, state machine data or other input into sequences of detailed circuit-level operations. It separates the machine instructions from the underlying electronics so that instructions can be designed and altered more freely. It also facilitates the building of complex multi-step instructions, while reducing the complexity of computer circuits. Writing microcode is often called ...more...

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Montecito (processor)

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Montecito (processor)

Montecito is the code-name of a major release of Intel's Itanium 2 Processor Family (IPF), which implements the Intel Itanium architecture on a dual-core processor. It was officially launched by Intel on July 18, 2006 as the "Dual-Core Intel Itanium 2 processor". According to Intel, Montecito doubles performance versus the previous, single-core Itanium 2 processor, and reduces power consumption by about 20%.[1] It also adds multi-threading capabilities (two threads per core), a greatly expanded cache subsystem (12 MB per core), and silicon support for virtualization. Architectural Features and Attributes Two cores per die 2-way coarse-grained multithreading per core (not simultaneous). Montecito-flavour of multi-threading is dubbed temporal, or TMT. This is also known as switch-on-event multithreading, or SoEMT. The two separate threads do not run simultaneously, but the core switches thread in case of a high latency event, like an L3 cache miss which would otherwise stall execution. By this technique, ...more...

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Befunge

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Befunge

Befunge is a stack-based, reflective, esoteric programming language. It differs from conventional languages in that programs are arranged on a two-dimensional grid. "Arrow" instructions direct the control flow to the left, right, up or down, and loops are constructed by sending the control flow in a cycle. It has been described as "a cross between Forth and Lemmings."[1] A worthy companion to INTERCAL; a computer language family which escapes the quotidian limitation of linear control flow and embraces program counters flying through multiple dimensions with exotic topologies. — Jargon File[2] History The language was originally created by Chris Pressey[3] in 1993 for the Amiga, as an attempt to devise a language which is as hard to compile as possible. Note that the p command allows for self-modifying code. Nevertheless, a number of compilers have subsequently been written. A number of extensions to the original "Befunge-93" specification also exist, most notably Funge-98, which extends the concept to ...more...

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SPARC

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SPARC

A Sun UltraSPARC II microprocessor (1997) SPARC, for Scalable Processor Architecture, is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from a number of vendors through the 1980s and 90s. The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in SMP and CC ...more...

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EKA2

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EKA2

EKA2 (EPOC Kernel Architecture 2) is the second-generation Symbian platform kernel.[1] Like its predecessor, EKA1, it has pre-emptive multithreading and full memory protection. The main differences are: Real-time guarantees (each API call is quick, but more importantly, time-bound) Multiple threads inside the kernel as well as outside Pluggable memory models, allowing better support for later generations of ARM instruction set. A "nanokernel" which provides the most basic OS facilities upon which other "personality layers" can be built The user-side interface of EKA2 is almost completely compatible with EKA1 -- though EKA1 has not been used since Symbian OS v8.1 (which was superseded in 2005). The main advantage of EKA2 was its ability to run full telephone signalling stacks. Previously, on Symbian phones, these had to run on a separate CPU. Such signalling stacks are extremely complex and rewriting them to work natively on Symbian OS is typically not an option. EKA2 therefore allows "personality la ...more...

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Interrupt

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Interrupt

interrupt sources and processor handling In system programming, an interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention. An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing. The processor responds by suspending its current activities, saving its state, and executing a function called an interrupt handler (or an interrupt service routine, ISR) to deal with the event. This interruption is temporary, and, after the interrupt handler finishes, the processor resumes normal activities.[1] There are two types of interrupts: hardware interrupts and software interrupts. Hardware interrupts are used by devices to communicate that they require attention from the operating system.[2] Internally, hardware interrupts are implemented using electronic alerting signals that are sent to the processor from an external device, which is either a part of the computer itself, su ...more...

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UltraSPARC T1

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UltraSPARC T1

Sun Microsystems' UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename "Niagara", is a multithreading, multicore CPU. Designed to lower the energy consumption of server computers, the CPU typically uses 72 W of power at 1.4 GHz. Afara Websystems pioneered a radical thread-heavy SPARC design. The company was purchased by Sun, and the intellectual property became the foundation of the CoolThreads line of processors, starting with the T1. The T1 is a new-from-the-ground-up SPARC microprocessor implementation that conforms to the UltraSPARC Architecture 2005 specification and executes the full SPARC V9 instruction set. Sun has produced two previous multicore processors (UltraSPARC IV and IV+), but UltraSPARC T1 is its first microprocessor that is both multicore and multithreaded. Security was built-in from the very first release on silicon, with hardware cryptographic units in the T1, unlike contemporary general purpose processor from competing vendors. The proc ...more...

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Open microprocessors

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Concurrent computing

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Concurrent computing

Concurrent computing is a form of computing in which several computations are executed during overlapping time periods—concurrently—instead of sequentially (one completing before the next starts). This is a property of a system—this may be an individual program, a computer, or a network—and there is a separate execution point or "thread of control" for each computation ("process"). A concurrent system is one where a computation can advance without waiting for all other computations to complete.[1] As a programming paradigm, concurrent computing is a form of modular programming, namely factoring an overall computation into subcomputations that may be executed concurrently. Pioneers in the field of concurrent computing include Edsger Dijkstra, Per Brinch Hansen, and C.A.R. Hoare. Introduction The concept of concurrent computing is frequently confused with the related but distinct concept of parallel computing,[2][3] although both can be described as "multiple processes executing during the same period of tim ...more...

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CPU time

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CPU time

CPU Time on Single CPU Multi Tasking System   CPU color time for program P1 CPU time (or process time) is the amount of time for which a central processing unit (CPU) was used for processing instructions of a computer program or operating system, as opposed to elapsed time, which includes for example, waiting for input/output (I/O) operations or entering low-power (idle) mode. The CPU time is measured in clock ticks or seconds. Often, it is useful to measure CPU time as a percentage of the CPU's capacity, which is called the CPU usage. CPU time and CPU usage have two main uses. The first use is to quantify the overall busyness of the system. When the CPU usage is above 70%, the user may experience lag. Such high CPU usage indicates insufficient processing power. Either the CPU needs to be upgraded, or the user experience reduced, for example, by switching to lower resolution graphics or reducing animations. The second use, with the advent of multi-tasking, is to quantify how the processor is shared betw ...more...

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Calling convention

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Calling convention

In computer science, a calling convention is an implementation-level (low-level) scheme for how subroutines receive parameters from their caller and how they return a result. Differences in various implementations include where parameters, return values, return addresses and scope links are placed, and how the tasks of preparing for a function call and restoring the environment afterward are divided between the caller and the callee. Calling conventions may be related to a particular programming language's evaluation strategy but most often are not considered part of it (or vice versa), as the evaluation strategy is usually defined on a higher abstraction level and seen as a part of the language rather than as a low-level implementation detail of a particular language's compiler. Variations Calling conventions may differ in: Where parameters, return values and return addresses are placed (in registers, on the call stack, a mix of both, or in other memory structures) The order in which actual arguments f ...more...

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IBM RS64

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IBM RS64

The IBM RS64 is a family of microprocessors that were used in the late 1990s in IBM's RS/6000 and AS/400 servers. These microprocessors implement the "Amazon", or "PowerPC-AS", instruction set architecture (ISA). Amazon is a superset of the PowerPC instruction set, with the addition of special features not in the PowerPC specification, mainly derived from POWER2 and the original AS/400 processor, and has been 64-bit from the start. The processors in this family are optimized for commercial workloads (integer performance, large caches, branches) and do not feature the strong floating point performance of the processors in the IBM POWER microprocessors family, its sibling. The RS64 family was phased out soon after the introduction of the POWER4, which was developed to unite the RS64 and POWER families. History In 1990 the Amazon project was started to create a common architecture that would host both AIX and OS/400. The AS/400 engineering team at IBM was designing a RISC instruction set to replace the CISC ...more...

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Microprocessor

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Microprocessor

Texas Instruments TMS1000. Intel 4004. Motorola 6800. A microprocessor is a computer processor that incorporates the functions of a central processing unit on a single integrated circuit (IC),[1] or at most a few integrated circuits.[2] The microprocessor is a multipurpose, clock driven, register based, digital-integrated circuit that accepts binary data as input, processes it according to instructions stored in its memory, and provides results as output. Microprocessors contain both combinational logic and sequential digital logic. Microprocessors operate on numbers and symbols represented in the binary numeral system. The integration of a whole CPU onto a single chip or on a few chips greatly reduced the cost of processing power, increasing efficiency. Integrated circuit processors are produced in large numbers by highly automated processes, resulting in a low per-unit cost. Single-chip processors increase reliability because there are many fewer electrical connections to fail. As microprocessor des ...more...

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Jacquard loom

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Jacquard loom

This portrait of Jacquard was woven in silk on a Jacquard loom and required 24,000 punched cards to create (1839). It was only produced to order. Charles Babbage owned one of these portraits; it inspired him in using perforated cards in his analytical engine.[1] It is in the collection of the Science Museum in London, England.[2] The Jacquard machine (French: ) is a device fitted to a power loom that simplifies the process of manufacturing textiles with such complex patterns as brocade, damask and matelassé.[3] It was invented by Joseph Marie Jacquard in 1804.[4] The loom was controlled by a "chain of cards"; a number of punched cards laced together into a continuous sequence.[5] Multiple rows of holes were punched on each card, with one complete card corresponding to one row of the design. Several such paper cards, generally white in color, can be seen in the images below. Chains, like Bouchon's earlier use of paper tape, allowed sequences of any length to be constructed, not limited by the size of a card. ...more...

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