No instruction set computing

No instruction set computing (NISC) is a computing architecture and compiler technology for designing highly efficient custom processors and hardware accelerators by allowing a compiler to have low-level control of hardware resources.

Overview

NISC is a statically-scheduled horizontal nanocoded architecture (SSHNA). The term "statically scheduled" means that the operation scheduling and hazard handling are done by a compiler. The term "horizontal nanocoded" means that NISC does not have any predefined instruction set or microcode. The compiler generates nanocodes which directly control functional units, registers and multiplexers of a given datapath. Giving low-level control to the compiler enables better utilization of datapath resources, which ultimately result in better performance. The benefits of NISC technology are:

  • Simpler controller: no hardware scheduler, no instruction decoder
  • Better performance: more flexible architecture, better resource utilization
  • Easier to design: no need for designing instruction-sets

The instruction set and controller of processors are the most tedious and time-consuming parts to design. By eliminating these two, design of custom processing elements become significantly easier.

Furthermore, the datapath of NISC processors can even be generated automatically for a given application. Therefore, designer's productivity is improved significantly.

Since NISC datapaths are very efficient and can be generated automatically, NISC technology is comparable to high level synthesis (HLS) or C to HDL synthesis approaches. In fact, one of the benefits of this architecture style is its capability to bridge these two technologies (custom processor design and HLS).

History

In the past, microprocessor design technology evolved from complex instruction set computer (CISC) to reduced instruction set computer (RISC). In the early days of the computer industry, compiler technology did not exist and programming was done in assembly language. To make programming easier, computer architects created complex instructions which were direct representations of high level functions of high level programming languages. Another force that encouraged instruction complexity was the lack of large memory blocks.

As compiler and memory technologies advanced, RISC architectures were introduced. RISC architectures need more instruction memory and require a compiler to translate high-level languages to RISC assembly code. Further advancement of compiler and memory technologies leads to emerging very long instruction word (VLIW) processors, where the compiler controls the schedule of instructions and handles data hazards.

NISC is a successor of VLIW processors. In NISC, the compiler has both horizontal and vertical control of the operations in the datapath. Therefore, the hardware is much simpler. However the control memory size is larger than the previous generations. To address this issue, low-overhead compression techniques can be used.

See also
Further reading
  • Chapter 2. Designing Embedded Processors: A Low Power Perspective: By: Jörg Henkel, Sri Parameswaran. ASIN 1402058683.

Continue Reading...
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IBM 650

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IBM 650

Part of the first IBM 650 computer in Norway (1959), known as "EMMA". 650 Console Unit (right, an exterior side panel is missing), 533 Card Read Punch unit (middle, input-output). 655 Power Unit is missing. Punched card sorter (left, not part of the 650). Now at Norwegian Museum of Science and Technology in Oslo. IBM 650 at Texas A&M University. The IBM 533 Card Read Punch unit is on the right. IBM 650 console panel, showing bi-quinary indicators. (At House for the History of IBM Data Processing (closed), Sindelfingen) Close-up of bi-quinary indicators The IBM 650 Magnetic Drum Data-Processing Machine is one of IBM's early computers, and the world’s first mass-produced computer.[1][2] It was announced in 1953 and in 1956 enhanced as the IBM 650 RAMAC with the addition of up to four disk storage units.[3] Almost 2,000 systems were produced, the last in 1962.[4] Support for the 650 and its component units was withdrawn in 1969. The 650 was a two-address, bi-quinary coded decimal comput ...more...

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Hybrid-core computing

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Hybrid-core computing

Hybrid-core computing is the technique of extending a commodity instruction set architecture (e.g. x86) with application-specific instructions to accelerate application performance. It is a form of heterogeneous computing[1] wherein asymmetric computational units coexist with a "commodity" processor. Hybrid-core processing differs from general heterogeneous computing in that the computational units share a common logical address space, and an executable is composed of a single instruction stream—in essence a contemporary coprocessor. The instruction set of a hybrid-core computing system contains instructions that can be dispatched either to the host instruction set or to the application-specific hardware. Typically, hybrid-core computing is best deployed where the predominance of computational cycles are spent in a few identifiable kernels, as is often seen in high-performance computing applications. Acceleration is especially pronounced when the kernel’s logic maps poorly to a sequence of commodity process ...more...

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Binary translation

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Binary translation

In computing, binary translation is a form of binary recompilation where sequences of instructions are translated from a source instruction set to the target instruction set. In some cases such as instruction set simulation, the target instruction set may be the same as the source instruction set, providing testing and debugging features such as instruction trace, conditional breakpoints and hot spot detection. The two main types are static and dynamic binary translation. Translation can be done in hardware (for example, by circuits in a CPU) or in software (e.g. run-time engines, statical recompiler, emulators). Motivation Motivation for using the complex process of binary translation is either that a compilation of the source code to the destination platform or instruction set is not available (or technically problematic) or when the source code is plainly not available anymore (Abandonware). Performance-wise static recompilations have the potential to achieve a better performance than real emulation ap ...more...

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Computer hardware

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Computer hardware

PDP-11 CPU board Computer hardware includes the physical parts or components of a computer, such as the central processing unit, monitor, keyboard, computer data storage, graphic card, sound card and motherboard.[1] By contrast, software is instructions that can be stored and run by hardware. Hardware is directed by the software to execute any command or instruction. A combination of hardware and software forms a usable computing system. Von Neumann architecture Von Neumann architecture scheme The template for all modern computers is the Von Neumann architecture, detailed in a 1945 paper by Hungarian mathematician John von Neumann. This describes a design architecture for an electronic digital computer with subdivisions of a processing unit consisting of an arithmetic logic unit and processor registers, a control unit containing an instruction register and program counter, a memory to store both data and instructions, external mass storage, and input and output mechanisms.[2] The meaning of the term ha ...more...

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Pipeline (computing)

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Pipeline (computing)

In computing, a pipeline, also known as a data pipeline,[1] is a set of data processing elements connected in series, where the output of one element is the input of the next one. The elements of a pipeline are often executed in parallel or in time-sliced fashion. Some amount of buffer storage is often inserted between elements. Computer-related pipelines include: Instruction pipelines, such as the classic RISC pipeline, which are used in central processing units (CPUs) to allow overlapping execution of multiple instructions with the same circuitry. The circuitry is usually divided up into stages and each stage processes a specific part of one instruction at a time, passing the partial results to the next stage. Examples of stages are instruction decode, arithmetic/logic and register fetch. Graphics pipelines, found in most graphics processing units (GPUs), which consist of multiple arithmetic units, or complete CPUs, that implement the various stages of common rendering operations (perspective projecti ...more...

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Interrupt flag

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Interrupt flag

IF (Interrupt Flag) is a system flag bit in the x86 architecture's FLAGS register, which determines whether or not the CPU will handle maskable hardware interrupts.[1] The bit, which is bit 9 of the FLAGS register, may be set or cleared by programs with sufficient privileges, as usually determined by the Operating System. If the flag is set to 1, maskable hardware interrupts will be handled. If cleared (set to 0), such interrupts will be ignored. IF does not affect the handling of non-maskable interrupts or software interrupts generated by the INT instruction. Setting and clearing The flag may be set or cleared using the CLI (Clear Interrupts), STI (Set Interrupts) and POPF (Pop Flags) instructions. CLI clears IF (sets to 0), while STI sets IF to 1. POPF pops 16 bits off the stack into the FLAGS register, which means IF will be set or cleared based on the ninth bit on the top of the stack.[1] Privilege level In all three cases, only privileged applications (usually the OS kernel) may modify IF. Note tha ...more...

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Microarchitecture

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Microarchitecture

Intel Core microarchitecture In computer engineering, microarchitecture, also called computer organization and sometimes abbreviated as µarch or uarch, is the way a given instruction set architecture (ISA), is implemented in a particular processor.[1] A given ISA may be implemented with different microarchitectures;[2][3] implementations may vary due to different goals of a given design or due to shifts in technology.[4] Computer architecture is the combination of microarchitecture and instruction set architecture. Relation to instruction set architecture A microarchitecture organized around a single bus The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machin ...more...

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Visual Instruction Set

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Visual Instruction Set

Visual Instruction Set, or VIS, is a SIMD instruction set extension for SPARC V9 microprocessors developed by Sun Microsystems. There are five versions of VIS: VIS 1, VIS 2, VIS 2+, VIS 3 and VIS 4.[1] History VIS 1 was introduced in 1994 and was first implemented by Sun in their UltraSPARC microprocessor (1995) and by Fujitsu in their SPARC64 GP microprocessors (2000). VIS 2 was first implemented by the UltraSPARC III. All subsequent UltraSPARC and SPARC64 microprocessors implement the instruction set. VIS 3 was first implemented in the SPARC T4 microprocessor. VIS 4 was first implemented in the SPARC M7 microprocessor. Differences vs x86 VIS is not an instruction toolkit like Intel's MMX and SSE. MMX has only 8 registers shared with the FPU stack, while SPARC processors have 32 registers, also aliased to the double-precision (64-bit) floating point registers. As with the SIMD instruction set extensions on other RISC processors, VIS strictly conforms to the main principle of RISC: keep the instructio ...more...

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FR-V (microprocessor)

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FR-V (microprocessor)

The Fujitsu FR-V (Fujitsu RISC-VLIW) is one of the very few processors ever able to process both a very long instruction word (VLIW) and vector processor instructions at the same time, increasing throughput with high parallel computing while increasing performance per watt and hardware efficiency. The family was presented in 1999.[1] Its design was influenced by the VPP500/5000 models of the Fujitsu VP/2000 vector processor supercomputer line.[2] Featuring a 1–8 way very long instruction word (VLIW, Multiple Instruction Multiple Data (MIMD), up to 256 bit) instruction set it additionally uses a 4-way single instruction, multiple data (SIMD) vector processor core. A 32-bit RISC instruction set in the superscalar core is combined with most variants integrating a dual 16-bit media processor also in VLIW and vector architecture. Each processor core is superpipelined as well as 4-unit superscalar. A typical integrated circuit integrates a system on a chip and further multiplies speed by integrating multiple core ...more...

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Computer

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Computer

A computer is a device that can be instructed to carry out sequences of arithmetic or logical operations automatically via computer programming. Modern computers have the ability to follow generalized sets of operations, called programs. These programs enable computers to perform an extremely wide range of tasks. Computers are used as control systems for a wide variety of industrial and consumer devices. This includes simple special purpose devices like microwave ovens and remote controls, factory devices such as industrial robots and computer-aided design, and also general purpose devices like personal computers and mobile devices such as smartphones. Early computers were only conceived as calculating devices. Since ancient times, simple manual devices like the abacus aided people in doing calculations. Early in the Industrial Revolution, some mechanical devices were built to automate long tedious tasks, such as guiding patterns for looms. More sophisticated electrical machines did specialized analog calcu ...more...

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Qualcomm Hexagon

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Qualcomm Hexagon

Hexagon (QDSP6) is the brand for a family of 32-bit multi-threaded microarchitectures implementing the same instruction set for a digital signal processor (DSP) developed by Qualcomm. According to 2012 estimation, Qualcomm shipped 1.2 billion DSP cores inside its system on a chip (SoCs) (average 2.3 DSP core per SoC) in 2011 year, and 1.5 billion cores were planned for 2012, making the QDSP6 the most shipped architecture of DSP[2] (CEVA had around 1 billion of DSP cores shipped in 2011 with 90% of IP-licenseable DSP market[3]). The Hexagon architecture is designed to deliver performance with low power over a variety of applications. It has features such as hardware assisted multithreading, privilege levels, Very Long Instruction Word (VLIW), Single Instruction, Multiple Data (SIMD),[4][5] and instructions geared toward efficient signal processing. The CPU is capable of in-order dispatching up to 4 instructions (the packet) to 4 Execution Units every clock.[6][7] Hardware multithreading is implemented as barr ...more...

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DEC Alpha

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DEC Alpha

DEC Alpha AXP 21064 microprocessor die photo Package for DEC Alpha AXP 21064 microprocessor Alpha AXP 21064 bare die mounted on a business card with some statistics Compaq Alpha 21264C Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computing (RISC) instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC), designed to replace their 32-bit VAX complex instruction set computer (CISC) ISA. Alpha was implemented in microprocessors originally developed and fabricated by DEC. These microprocessors were most prominently used in a variety of DEC workstations and servers, which eventually formed the basis for almost all of their mid-to-upper-scale lineup. Several third-party vendors also produced Alpha systems, including PC form factor motherboards. Operating systems that supported Alpha included OpenVMS (previously known as OpenVMS AXP), Tru64 UNIX (previously known as DEC OSF/1 AXP and Digital UNIX), Windows NT (discontinued after NT 4.0; and pre-releas ...more...

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MMIX

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MMIX

MMIX (pronounced em-mix) is a 64-bit reduced instruction set computing (RISC) architecture designed by Donald Knuth, with significant contributions by John L. Hennessy (who contributed to the design of the MIPS architecture) and Richard L. Sites (who was an architect of the Alpha architecture). Knuth has said that "MMIX is a computer intended to illustrate machine-level aspects of programming. In my books The Art of Computer Programming, it replaces MIX, the 1960s-style machine that formerly played such a role… I strove to design MMIX so that its machine language would be simple, elegant, and easy to learn. At the same time I was careful to include all of the complexities needed to achieve high performance in practice, so that MMIX could in principle be built and even perhaps be competitive with some of the fastest general-purpose computers in the marketplace."[1] Architecture MMIX is a big-endian 64-bit reduced instruction set computer (RISC), with 256 64-bit general-purpose registers, 32 64-bit special-pu ...more...

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Computing

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Computing

A difference engine: computing the solution to a polynomial function Computer laboratory, Moody Hall, James Madison University, 2003 A rack of servers from 2006 Computing is any activity that uses computers. It includes developing hardware and software, and using computers to manage and process information, communicate and entertain. Computing is a critically important, integral component of modern industrial technology. Major computing disciplines include computer engineering, software engineering, computer science, information systems, and information technology. Definitions The ACM Computing Curricula 2005[1] defined "computing" as follows: "In a general way, we can define computing to mean any goal-oriented activity requiring, benefiting from, or creating computers. Thus, computing includes designing and building hardware and software systems for a wide range of purposes; processing, structuring, and managing various kinds of information; doing scientific studies using computers; making comput ...more...

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Elbrus 2000

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Elbrus 2000

The Elbrus 2000, E2K (Russian: Эльбрус 2000) is a Russian 512-bit wide VLIW microprocessor developed by Moscow Center of SPARC Technologies (MCST) and fabricated by TSMC. It supports two instruction set architecture (ISA): Elbrus VLIW Intel x86 (a complete, system-level implementation with a software dynamic binary translation virtual machine, similar to Transmeta Crusoe) Thanks to its unique architecture Elbrus 2000 can execute 20 instructions per clock, so even with its modest clock speed it can compete with much faster clocked superscalar microprocessors when running in native VLIW mode.[1][2] For security reasons the Elbrus 2000 architecture implements dynamic data type-checking during execution. In order to prevent unauthorized access, each pointer has additional type information that is verified when the associated data is accessed.[3] Supported operating systems GNU/Linux compiled for Elbrus ISA GNU/Linux compiled for x86 ISA Windows 95 Windows 2000 Windows XP QNX Elbrus 2000 info ...more...

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KISS principle

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KISS principle

KISS is an acronym for "Keep it simple, stupid" as a design principle noted by the U.S. Navy in 1960.[1][2] The KISS principle states that most systems work best if they are kept simple rather than made complicated; therefore simplicity should be a key goal in design, and that unnecessary complexity should be avoided. The phrase has been associated with aircraft engineer Kelly Johnson.[3] The term "KISS principle" was in popular use by 1970.[4] Variations on the phrase include: "Keep it simple, silly", "keep it short and simple", "keep it simple and straightforward",[5] "keep it small and simple" and "keep it stupid simple".[6] Origin The acronym was reportedly coined by Kelly Johnson, lead engineer at the Lockheed Skunk Works (creators of the Lockheed U-2 and SR-71 Blackbird spy planes, among many others).[3] While popular usage has transcribed it for decades as "Keep it simple, stupid", Johnson transcribed it as "Keep it simple stupid" (no comma), and this reading is still used by many authors.[7] There ...more...

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Heterogeneous computing

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Heterogeneous computing

Heterogeneous computing refers to systems that use more than one kind of processor or cores. These systems gain performance or energy efficiency not just by adding the same type of processors, but by adding dissimilar coprocessors, usually incorporating specialized processing capabilities to handle particular tasks.[1] Heterogeneity Usually heterogeneity in the context of computing referred to different instruction-set architectures (ISA), where the main processor has one and other processors have another - usually a very different - architecture (maybe more than one), not just a different microarchitecture (floating point number processing is a special case of this - not usually referred to as heterogeneous). For example, ARM big.LITTLE is an exception where the ISAs of cores are the same and heterogeneity refers to the speed of different microarchitectures of the same ISA,[2] then making it more like a symmetric multiprocessor (SMP). In the past heterogeneous computing meant different ISAs had to be han ...more...

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TOP500

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TOP500

TOP500 project logo The TOP500 project ranks and details the 500 most powerful non-distributed computer systems in the world. The project was started in 1993 and publishes an updated list of the supercomputers twice a year. The first of these updates always coincides with the International Supercomputing Conference in June, and the second is presented at the ACM/IEEE Supercomputing Conference in November. The project aims to provide a reliable basis for tracking and detecting trends in high-performance computing and bases rankings on HPL,[1] a portable implementation of the high-performance LINPACK benchmark written in Fortran for distributed-memory computers. In the most recent list (June 2018), the American Summit is the world's most powerful supercomputer, reaching 122.3 petaFLOPS on the LINPACK benchmarks. The TOP500 list is compiled by Jack Dongarra of the University of Tennessee, Knoxville, Erich Strohmaier and Horst Simon of the National Energy Research Scientific Computing Center (NERSC) and Lawren ...more...

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History of general-purpose CPUs

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History of general-purpose CPUs

The history of general-purpose CPUs is a continuation of the earlier history of computing hardware. 1950s: Early designs A Vacuum tube module from early 700 series IBM computers In the early 1950s, each computer design was unique. There were no upward-compatible machines or computer architectures with multiple, differing implementations. Programs written for one machine would run on no other kind, even other kinds from the same company. This was not a major drawback then because no large body of software had been developed to run on computers, so starting programming from scratch was not seen as a large barrier. The design freedom of the time was very important, for designers were very constrained by the cost of electronics, and only starting to explore how a computer could best be organized. Some of the basic features introduced during this period included index registers (on the Ferranti Mark 1), a return address saving instruction (UNIVAC I), immediate operands (IBM 704), and detecting invalid operat ...more...

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AVX-512

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AVX-512

AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and supported in Intel's Xeon Phi x200 (Knights Landing)[1] and Skylake-X CPUs; this includes the Core-X series (excluding the Core i5-7640X and Core i7-7740X), as well as the new Xeon Scalable Processor Family and Xeon D-2100 Embedded Series[2]. AVX-512 is not the first 512-bit SIMD instruction set that Intel has introduced in processors. The earlier 512-bit SIMD instructions used in Xeon Phi coprocessors, derived from Intel's Larrabee project, are similar but not binary compatible and only partially source compatible.[1] AVX-512 consists of multiple extensions that are not all meant to be supported by all processors implementing them. This policy is a departure from the historical requirement of implementing the entire instruction block. Only the core extension AVX-512F (AVX-512 Foundation) is required by all implementations. Instruction se ...more...

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Illegal opcode

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Illegal opcode

A human generated illegal instruction signal. An illegal opcode, also called an undocumented instruction, is an instruction to a CPU that is not mentioned in any official documentation released by the CPU's designer or manufacturer, which nevertheless has an effect. Illegal opcodes were common on older CPUs designed during the 1970s, such as the MOS Technology 6502, Intel 8086, and the Zilog Z80. On these older processors, many exist as a side effect of the wiring of transistors in the CPU, and usually combine functions of the CPU that were not intended to be combined. On old and modern processors, there are also instructions intentionally included in the processor by the manufacturer, but that are not documented in any official specification. While most accidental illegal instructions have useless or even highly undesirable effects (such as crashing the computer), a few might by accident do something that can be useful in certain situations. Such instructions were sometimes exploited in computer games of ...more...

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Cache control instruction

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Cache control instruction

In computing, a cache control instruction is a hint embedded in the instruction stream of a processor intended to improve the performance of hardware caches, using foreknowledge of the memory access pattern supplied by the programmer or compiler.[1] They may reduce cache pollution, reduce bandwidth requirement, bypass latencies, by providing better control over the working set. Most cache control instructions do not affect the semantics of a program, although some can. Examples Several such instructions, with variants, are supported by several processor instruction set architectures, such as ARM, MIPS, PowerPC, and x86. Prefetch Also termed data cache block touch, the effect is to request loading the cache line associated with a given address. This is performed by the PREFETCH instruction in the x86 instruction set. Some variants bypass higher levels of the cache hierarchy, which is useful in a 'streaming' context for data that is traversed once, rather than held in the working set. The prefetch should oc ...more...

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Fisc (disambiguation)

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Fisc (disambiguation)

Look up fisc in Wiktionary, the free dictionary. Fisc may refer to: fisc, taxes paid in kind, especially those of the Frankish kings, or a knight's money holder As an acronym, FISC may refer to: Farm and Industry Short Course, a farmer-based program through the University of Wisconsin-Madison College of Agricultural and Life Sciences fast instruction set computer, a term used in computer science describing a CPU where the notion of complex instruction set computing (CISC) and reduced instruction set computing (RISC) have become deprecated Fleet and Industrial Supply Center, an archaic name for an installation of a NAVSUP Fleet Logistics Center maintained by the Naval Supply Systems Command of the United States Navy United States Foreign Intelligence Surveillance Court (also known as the FISA Court), a U.S. federal court See also fiscus, the personal treasury of the emperors of Rome ...more...

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Streaming SIMD Extensions

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Streaming SIMD Extensions

In computing, Streaming SIMD Extensions (SSE) is an SIMD instruction set extension to the x86 architecture, designed by Intel and introduced in 1999 in their Pentium III series of processors shortly after the appearance of AMD's 3DNow!. SSE contains 70 new instructions, most of which work on single precision floating point data. SIMD instructions can greatly increase performance when exactly the same operations are to be performed on multiple data objects. Typical applications are digital signal processing and graphics processing. Intel's first IA-32 SIMD effort was the MMX instruction set. MMX had two main problems: it re-used existing x87 floating point registers making the CPU unable to work on both floating point and SIMD data at the same time, and it only worked on integers. SSE floating point instructions operate on a new independent register set (the XMM registers), and it adds a few integer instructions that work on MMX registers. SSE was subsequently expanded by Intel to SSE2, SSE3, SSSE3, and SSE4 ...more...

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SSE4

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SSE4

SSE4 (Streaming SIMD Extensions 4) is a SIMD CPU instruction set used in the Intel Core microarchitecture and AMD K10 (K8L). It was announced on 27 September 2006 at the Fall 2006 Intel Developer Forum, with vague details in a white paper;[1] more precise details of 47 instructions became available at the Spring 2007 Intel Developer Forum in Beijing, in the presentation.[2] SSE4 is fully compatible with software written for previous generations of Intel 64 and IA-32 architecture microprocessors. All existing software continues to run correctly without modification on microprocessors that incorporate SSE4, as well as in the presence of existing and new applications that incorporate SSE4.[3] SSE4 subsets Intel SSE4 consists of 54 instructions. A subset consisting of 47 instructions, referred to as SSE4.1 in some Intel documentation, is available in Penryn. Additionally, SSE4.2, a second subset consisting of the 7 remaining instructions, is first available in Nehalem-based Core i7. Intel credits feedback from ...more...

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LLVM

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LLVM

The LLVM compiler infrastructure project is a "collection of modular and reusable compiler and toolchain technologies"[3] used to develop compiler front ends and back ends. LLVM is written in C++ and is designed for compile-time, link-time, run-time, and "idle-time" optimization of programs written in arbitrary programming languages. Originally implemented for C and C++, the language-agnostic design of LLVM has since spawned a wide variety of front ends: languages with compilers that use LLVM include ActionScript, Ada, C#,[4][5][6] Common Lisp, Crystal, CUDA, D, Delphi, Fortran, Graphical G Programming Language,[7] Halide, Haskell, Java bytecode, Julia, Kotlin, Lua, Objective-C, OpenGL Shading Language, Pony,[8] Python, R, Ruby,[9] Rust, Scala,[10] Swift, and Xojo. History The LLVM project started in 2000 at the University of Illinois at Urbana–Champaign, under the direction of Vikram Adve and Chris Lattner. LLVM was originally developed as a research infrastructure to investigate dynamic compilation techn ...more...

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ARC (processor)

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ARC (processor)

ARC (Argonaut RISC Core) embedded processors are a family of 32-bit central processing units (CPUs) originally designed by ARC International. They are widely used in System on a chip (SoC) devices for storage, home, mobile, automotive, and Internet of things (IoT) applications. ARC processors have been licensed by more than 200 organizations and are shipped in more than 1.5 billion products per year.[1] ARC processors are now part of the Synopsys DesignWare series, and can be optimized for a wide range of uses. Designers can differentiate their products by using patented configuration technology to tailor each ARC processor instance to meet specific performance, power and area requirements. The ARC processors are also extendable, allowing designers to add their own custom instructions that can significantly increase performance or reduce power consumption. ARC processors are reduced instruction set computing (RISC) processors, and employ the 16-/32-bit ARCompact instruction set architecture (ISA) that provi ...more...

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Itanium

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Itanium

Itanium ( eye-TAY-nee-əm) is a family of 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). Intel markets the processors for enterprise servers and high-performance computing systems. The Itanium architecture originated at Hewlett-Packard (HP), and was later jointly developed by HP and Intel. Itanium-based systems have been produced by HP (the HP Integrity Servers line) and several other manufacturers. In 2008, Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power Architecture, and SPARC.[1] In February 2017, Intel released the current generation, Kittson, to test customers, and in May began shipping in volume.[2] It is the last processor of the Itanium family.[3][4] History Itanium Server Sales forecast history[5][6] Development: 1989–2000 In 1989, HP determined that Reduced Instruction Set Computing (RISC) architectures were approaching a processing limit at one instruction per cycle. HP r ...more...

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NOP

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NOP

In computer science, a NOP, no-op, or NOOP (pronounced "no op"; short for no operation) is an assembly language instruction, programming language statement, or computer protocol command that does nothing. Machine set of directions Some computer instruction sets include an instruction whose explicit purpose is to not change the state of any of the programmer-accessible registers, status flags, or memory. It often takes a well-defined number of clock cycles to execute. In other instruction sets, a NOP can be simulated by executing an instruction having operands that cause the same effect; e.g., on the SPARC processor, the instruction sethi 0, %g0 is the recommended solution. A NOP is most commonly used for timing purposes, to force memory alignment, to prevent hazards, to occupy a branch delay slot, to render void an existing instruction such as a jump, or as a place-holder to be replaced by active instructions later on in program development (or to replace removed instructions when reorganizing would be pro ...more...

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SPARC

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SPARC

A Sun UltraSPARC II microprocessor (1997) SPARC, for Scalable Processor Architecture, is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems. Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s. First released in 1987, SPARC was one of the most successful early commercial RISC systems, and its success led to the introduction of similar RISC designs from a number of vendors through the 1980s and 90s. The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors. SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992. SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995. Later, SPARC processors were used in SMP and CC ...more...

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1985 introductions

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Processor design

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Processor design

Processor design is the design engineering task of creating a processor, a component of computer hardware. It is a subfield of computer engineering (design, development and implementation) and electronics engineering (fabrication). The design process involves choosing an instruction set and a certain execution paradigm (e.g. VLIW or RISC) and results in a microarchitecture, which might be described in e.g. VHDL or Verilog. For microprocessor design, this description is then manufactured employing some of the various semiconductor device fabrication processes, resulting in a die which is bonded onto a chip carrier. This chip carrier is then soldered onto, or inserted into a socket on, a printed circuit board (PCB). The mode of operation of any processor is the execution of lists of instructions. Instructions typically include those to compute or manipulate data values using registers, change or retrieve values in read/write memory, perform relational tests between data values and to control program flow. Det ...more...

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Subroutine

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Subroutine

In computer programming, a subroutine is a sequence of program instructions that performs a specific task, packaged as a unit. This unit can then be used in programs wherever that particular task should be performed. Subprograms may be defined within programs, or separately in libraries that can be used by multiple programs. In different programming languages, a subroutine may be called a procedure, a function, a routine, a method, or a subprogram. The generic term callable unit is sometimes used.[1] The name subprogram suggests a subroutine behaves in much the same way as a computer program that is used as one step in a larger program or another subprogram. A subroutine is often coded so that it can be started (called) several times and from several places during one execution of the program, including from other subroutines, and then branch back (return) to the next instruction after the call, once the subroutine's task is done. Maurice Wilkes, David Wheeler, and Stanley Gill are credited with the inventi ...more...

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University of Cambridge Computer Laboratory

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Multi-core processor

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Multi-core processor

Diagram of a generic dual-core processor with CPU-local level-1 caches and a shared, on-die level-2 cache. An Intel Core 2 Duo E6750 dual-core processor. An AMD Athlon X2 6400+ dual-core processor. A multi-core processor is a single computing component with two or more independent processing units called cores, which read and execute program instructions.[1] The instructions are ordinary CPU instructions (such as add, move data, and branch) but the single processor can run multiple instructions on separate cores at the same time, increasing overall speed for programs amenable to parallel computing.[2] Manufacturers typically integrate the cores onto a single integrated circuit die (known as a chip multiprocessor or CMP) or onto multiple dies in a single chip package. The microprocessors currently used in almost all personal computers are multi-core. A multi-core processor implements multiprocessing in a single physical package. Designers may couple cores in a multi-core device tightly or loosely. For ...more...

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Digital signal processing

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Research SDMN

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Multiply–accumulate operation

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Multiply–accumulate operation

In computing, especially digital signal processing, the multiply–accumulate operation is a common step that computes the product of two numbers and adds that product to an accumulator. The hardware unit that performs the operation is known as a multiplier–accumulator (MAC, or MAC unit); the operation itself is also often called a MAC or a MAC operation. The MAC operation modifies an accumulator a:   a ← a + ( b × c ) {\displaystyle \ a\leftarrow a+(b\times c)} When done with floating point numbers, it might be performed with two roundings (typical in many DSPs), or with a single rounding. When performed with a single rounding, it is called a fused multiply–add (FMA) or fused multiply–accumulate (FMAC). Modern computers may contain a dedicated MAC, consisting of a multiplier implemented in combinational logic followed by an adder and an accumulator register that stores the result. The output of the register is fed back to one input of the adder, so that on each clock cycle, the output of the multipl ...more...

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Digital signal processing

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Central processing unit

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Central processing unit

An Intel 80486DX2 CPU, as seen from above Bottom side of an Intel 80486DX2, showing its pins A central processing unit (CPU) is the electronic circuitry within a computer that carries out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions. The computer industry has used the term "central processing unit" at least since the early 1960s.[1] Traditionally, the term "CPU" refers to a processor, more specifically to its processing unit and control unit (CU), distinguishing these core elements of a computer from external components such as main memory and I/O circuitry.[2] The form, design, and implementation of CPUs have changed over the course of their history, but their fundamental operation remains almost unchanged. Principal components of a CPU include the arithmetic logic unit (ALU) that performs arithmetic and logic operations, processor registers that supply operands to the ALU and store the result ...more...

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Central processing unit

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Elliott 803

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Elliott 803

Parts from an Elliott 803B The Elliott 803 is a small, medium-speed transistor digital computer which was manufactured by the British company Elliott Brothers in the 1960s. About 211 were built.[1] History The 800 series started with the 801, a one-off test machine built in 1957. The 802 was a production model but only seven were sold between 1958 and 1961. The short-lived 803A was built in 1959 and first delivered in 1960; the 803B was built in 1960 and first delivered in 1961. Over 200 Elliott 803 computers were delivered to customers, at a price of about £29,000 in 1960 [2] (roughly equivalent to £613,000 in 2016[3]). The majority of sales were the 803B version with more parallel paths internally, larger memory and hardware floating-point operations. In 2010, two complete Elliott 803 computers survive. One is owned by the Science Museum (London) but it is not on display to the public. The second one is owned by The National Museum of Computing (TNMoC) at Bletchley Park and is fully functional.[4] Both ...more...

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Early British computers

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SSSE3

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SSSE3

Supplemental Streaming SIMD Extensions 3 (SSSE3 or SSE3S) is a SIMD instruction set created by Intel and is the fourth iteration of the SSE technology. History SSSE3 was first introduced with Intel processors based on the Core microarchitecture on 26 June 2006 with the "Woodcrest" Xeons. SSSE3 has been referred to by the codenames Tejas New Instructions (TNI) or Merom New Instructions (MNI) for the first processor designs intended to support it. Functionality SSSE3 contains 16 new discrete instructions. Each instruction can act on 64-bit MMX or 128-bit XMM registers. Therefore, Intel's materials refer to 32 new instructions. According to Intel: SSSE3 provide 32 instructions (represented by 14 mnemonics) to accelerate computations on packed integers. These include:[1] Twelve instructions that perform horizontal addition or subtraction operations. Six instructions that evaluate absolute values. Two instructions that perform multiply and add operations and speed up the evaluation of dot products. Tw ...more...

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Vector processor

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Vector processor

In computing, a vector processor or array processor is a central processing unit (CPU) that implements an instruction set containing instructions that operate on one-dimensional arrays of data called vectors, compared to scalar processors, whose instructions operate on single data items. Vector processors can greatly improve performance on certain workloads, notably numerical simulation and similar tasks. Vector machines appeared in the early 1970s and dominated supercomputer design through the 1970s into the 1990s, notably the various Cray platforms. The rapid fall in the price-to-performance ratio of conventional microprocessor designs led to the vector supercomputer's demise in the later 1990s. As of 2015 most commodity CPUs implement architectures that feature instructions for a form of vector processing on multiple (vectorized) data sets, typically known as SIMD (Single Instruction, Multiple Data). Common examples include Intel x86's MMX, SSE and AVX instructions, AMD's 3DNow! extensions, Sparc's VIS ex ...more...

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Central processing unit

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Instruction-level parallelism

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Instruction-level parallelism

Atanasoff–Berry computer, the first computer with parallel processing[1] Instruction-level parallelism (ILP) is a measure of how many of the instructions in a computer program can be executed simultaneously. There are two approaches to instruction level parallelism: Hardware Software Hardware level works upon dynamic parallelism whereas, the software level works on static parallelism. Dynamic parallelism means the processor decides at run time which instructions to execute in parallel, whereas static parallelism means the compiler decides which instructions to execute in parallel.[2] The Pentium processor works on the dynamic sequence of parallel execution, but the Itanium processor works on the static level parallelism. Consider the following program: e = a + b f = c + d m = e * f Operation 3 depends on the results of operations 1 and 2, so it cannot be calculated until both of them are completed. However, operations 1 and 2 do not depend on any other operation, so they can be calculated simul ...more...

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Parallel computing

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DMS-100

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DMS-100

Typical Northern Telecom DMS-100 Telephone Central Office Installation A DMS-100, in a CO located in France The DMS-100 Switch Digital Multiplex System (DMS) was a line of telephone exchange switches manufactured by Northern Telecom. Designed during the 1970s and released in 1979, it can control 100,000 telephone lines.[1] The purpose of the DMS-100 Switch is to provide local service and connections to the PSTN public telephone network. It is designed to deliver services over subscribers' telephone lines and trunks. It provides Plain Old Telephone Service (POTS), mobility management for cellular phone systems, sophisticated business services such as Automatic Call Distribution (ACD), Integrated Services Digital Network (ISDN), and Meridian Digital Centrex (MDC), formerly called Integrated Business Network (IBN). It also provides Intelligent Network functions (AIN, CS1-R, ETSI INAP). It is used in countries throughout the world. Much of the hardware used in the DMS-100, with the possible exception of ...more...

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Telephone exchange equipment

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Zilog Z80

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Zilog Z80

A CMOS Z80 in a Quad Flat Package A May 1976 advertisement for the Zilog Z-80 8-bit microprocessor The Z80 CPU is an 8-bit based microprocessor. It was introduced by Zilog in 1976 as the startup company's first product. The Z80 was conceived by Federico Faggin in late 1974 and developed by him and his then-11 employees at Zilog from early 1975 until March 1976, when the first fully working samples were delivered. With the revenue from the Z80, the company built its own chip factories and grew to over a thousand employees over the following two years.[2] The Zilog Z80 was a software-compatible extension and enhancement of the Intel 8080 and, like it, was mainly aimed at embedded systems. According to the designers, the primary targets for the Z80 CPU (and its optional support and peripheral ICs[3]) were products like intelligent terminals, high end printers and advanced cash registers as well as telecom equipment, industrial robots and other kinds of automation equipment. The Z80 was officially introduce ...more...

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Z80

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Computer cluster

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Computer cluster

Technicians working on a large Linux cluster at the Chemnitz University of Technology, Germany Sun Microsystems Solaris Cluster A computer cluster is a set of loosely or tightly connected computers that work together so that, in many respects, they can be viewed as a single system. Unlike grid computers, computer clusters have each node set to perform the same task, controlled and scheduled by software. The components of a cluster are usually connected to each other through fast local area networks, with each node (computer used as a server) running its own instance of an operating system. In most circumstances, all of the nodes use the same hardware[1] and the same operating system, although in some setups (e.g. using Open Source Cluster Application Resources (OSCAR)), different operating systems can be used on each computer, or different hardware.[2] Clusters are usually deployed to improve performance and availability over that of a single computer, while typically being much more cost-effective tha ...more...

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Quarterly journals

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* IT chronicle *

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Arithmetic logic unit

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Arithmetic logic unit

A symbolic representation of an ALU and its input and output signals, indicated by arrows pointing into or out of the ALU, respectively. Each arrow represents one or more signals. Control signals enter from the left and status signals exit on the right; data flows from top to bottom. An arithmetic logic unit (ALU) is a combinational digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. This is in contrast to a floating-point unit (FPU), which operates on floating point numbers. An ALU is a fundamental building block of many types of computing circuits, including the central processing unit (CPU) of computers, FPUs, and graphics processing units (GPUs). A single CPU, FPU or GPU may contain multiple ALUs. The inputs to an ALU are the data to be operated on, called operands, and a code indicating the operation to be performed; the ALU's output is the result of the performed operation. In many designs, the ALU also has status inputs or outputs, or both, which conv ...more...

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Central processing unit

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* IT chronicle *

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Ruby B. Lee

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Ruby B. Lee

Ruby Bei-Loh Lee is an American electrical engineer who works as the Forrest G. Hamrick Professor in Engineering at Princeton University.[1] Her contributions to computer architecture include work in reduced instruction set computing, embedded systems, and hardware support for computer security and digital media.[2] At Princeton, she is the director of the Princeton Architecture Laboratory for Multimedia and Security.[3] Tech executive Joel S. Birnbaum has called her "one of the top instruction-set architects in the world".[2] Education and career Lee graduated from Cornell University's College Scholar Program in 1973. She went to Stanford University for her graduate studies, earning a master's degree in computer science and computer engineering in 1975, and a doctorate in electrical engineering in 1980. After briefly teaching at Stanford, she joined Hewlett-Packard in 1981, eventually becoming a chief architect there in 1992, and holding a consulting faculty position at Stanford from 1989 until 1998. She m ...more...

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Fellow Members of the IEEE

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Branch (computer science)

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Branch (computer science)

A branch is an instruction in a computer program that can cause a computer to begin executing a different instruction sequence and thus deviate from its default behavior of executing instructions in order.[a] Branch (or branching, branched) may also refer to the act of switching execution to a different instruction sequence as a result of executing a branch instruction. A branch instruction can be either an unconditional branch, which always results in branching, or a conditional branch, which may or may not cause branching, depending on some condition. Branch instructions are used to implement control flow in program loops and conditionals (i.e., executing a particular sequence of instructions only if certain conditions are satisfied). Implementation Mechanically, a branch instruction can change the program counter (PC) of a CPU. The program counter is the memory address of the next instruction. Therefore, a branch can cause the CPU to begin fetching its instructions from a different sequence of memory cel ...more...

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Machine code

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CHIP-8

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CHIP-8

Screenshot of Pong implemented in CHIP-8 Telmac 1800 running CHIP-8 game Space Intercept (Joseph Weisbecker, 1978) CHIP-8 is an interpreted programming language, developed by Joseph Weisbecker. It was initially used on the COSMAC VIP and Telmac 1800 8-bit microcomputers in the mid-1970s. CHIP-8 programs are run on a CHIP-8 virtual machine. It was made to allow video games to be more easily programmed for these computers. Roughly twenty years after CHIP-8 was introduced, derived interpreters appeared for some models of graphing calculators (from the late 1980s onward, these handheld devices in many ways have more computing power than most mid-1970s microcomputers for hobbyists). An active community of users and developers existed in the late 1970s, beginning with ARESCO's "VIPer" newsletter whose first three issues revealed the machine code behind the CHIP-8 interpreter.[1] CHIP-8 applications There are a number of classic video games ported to CHIP-8, such as Pong, Space Invaders, Tetris, and Pac- ...more...

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Virtualization software

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Stanford MIPS

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Stanford MIPS

MIPS (an acronym for Microprocessor without Interlocked Pipeline Stages) was a research project conducted by John L. Hennessy at Stanford University between 1981 and 1984. MIPS investigated a type of instruction set architecture (ISA) now called Reduced Instruction Set Computer (RISC), its implementation as a microprocessor with very large scale integration (VLSI) semiconductor technology, and the effective exploitation of RISC architectures with optimizing compilers. MIPS, together with the IBM 801 and Berkeley RISC, were the three research projects that pioneered and popularized RISC technology in the mid-1980s. In recognition of the impact MIPS made on computing, Hennessey was awarded the IEEE John von Neumann Medal in 2000 by the IEEE (shared with David A. Patterson), the Eckert–Mauchly Award in 2001 by the Association for Computing Machinery, and the Seymour Cray Computer Engineering Award in 2001 by the IEEE Computer Society. The project was initiated in 1981 in response to reports of similar projects ...more...

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Instruction set architectures

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Turing completeness

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Turing completeness

In computability theory, a system of data-manipulation rules (such as a computer's instruction set, a programming language, or a cellular automaton) is said to be Turing complete or computationally universal if it can be used to simulate any Turing machine. The concept is named after English mathematician and computer scientist Alan Turing. A classic example is lambda calculus. A closely related concept is that of Turing equivalence – two computers P and Q are called equivalent if P can simulate Q and Q can simulate P. The Church–Turing thesis conjectures that any function whose values can be computed by an algorithm can be computed by a Turing machine, and therefore that if any real-world computer can simulate a Turing machine, it is Turing equivalent to a Turing machine. A universal Turing machine can be used to simulate any Turing machine and by extension the computational aspects of any possible real-world computer.[NB 1] To show that something is Turing complete, it is enough to show that it can be use ...more...

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Theory of computation

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Analytical Engine

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Analytical Engine

Trial model of a part of the Analytical Engine, built by Babbage, as displayed at the Science Museum (London)[1] The Analytical Engine was a proposed mechanical general-purpose computer designed by English mathematician and computer pioneer Charles Babbage.[2][3] It was first described in 1837 as the successor to Babbage's difference engine, a design for a mechanical computer.[4] The Analytical Engine incorporated an arithmetic logic unit, control flow in the form of conditional branching and loops, and integrated memory, making it the first design for a general-purpose computer that could be described in modern terms as Turing-complete.[5][6] In other words, the logical structure of the Analytical Engine was essentially the same as that which has dominated computer design in the electronic era.[3] Babbage was never able to complete construction of any of his machines due to conflicts with his chief engineer and inadequate funding.[7][8] It was not until the 1940s that the first general-purpose computers ...more...

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English inventions

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Turing machine

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Turing machine

Classes of automata A Turing machine is a mathematical model of computation that defines an abstract machine,[1] which manipulates symbols on a strip of tape according to a table of rules.[2] Despite the model's simplicity, given any computer algorithm, a Turing machine capable of simulating that algorithm's logic can be constructed.[3] The machine operates on an infinite[4] memory tape divided into discrete cells.[5] The machine positions its head over a cell and "reads" (scans)[6] the symbol there. Then, as per the symbol and its present place in a finite table[7] of user-specified instructions, the machine (i) writes a symbol (e.g., a digit or a letter from a finite alphabet) in the cell (some models allowing symbol erasure or no writing),[8] then (ii) either moves the tape one cell left or right (some models allow no motion, some models move the head),[9] then (iii) (as determined by the observed symbol and the machine's place in the table) either proceeds to a subsequent instruction or halts the compu ...more...

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Theoretical computer science

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